hwmon: (coretemp) Fix TjMax for Atom N450/D410/D510 CPUs

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From: Linux Kernel Mailing List
Date: Monday, January 11, 2010 - 11:59 am

Gitweb:     http://git.kernel.org/linus/1fe63ab47a617ee95f562eaa7ddbbc59981ff8c6
Commit:     1fe63ab47a617ee95f562eaa7ddbbc59981ff8c6
Parent:     c5114a1cd6d84b2b3144c1c3e093c80ca6c30f47
Author:     Yong Wang <yong.y.wang@linux.intel.com>
AuthorDate: Sun Jan 10 20:52:34 2010 +0100
Committer:  Jean Delvare <khali@linux-fr.org>
CommitDate: Sun Jan 10 20:52:34 2010 +0100

    hwmon: (coretemp) Fix TjMax for Atom N450/D410/D510 CPUs
    
    The max junction temperature of Atom N450/D410/D510 CPUs is 100 degrees
    Celsius. Since these CPUs are always coupled with Intel NM10 chipset in
    one package, the best way to verify whether an Atom CPU is N450/D410/D510
    is to check the host bridge device.
    
    Signed-off-by: Yong Wang <yong.y.wang@intel.com>
    Acked-by: Huaxu Wan <huaxu.wan@intel.com>
    Signed-off-by: Jean Delvare <khali@linux-fr.org>
---
 drivers/hwmon/Kconfig    |    2 +-
 drivers/hwmon/coretemp.c |   16 ++++++++++++++--
 2 files changed, 15 insertions(+), 3 deletions(-)

diff --git a/drivers/hwmon/Kconfig b/drivers/hwmon/Kconfig
index 46c3c56..435ae72 100644
--- a/drivers/hwmon/Kconfig
+++ b/drivers/hwmon/Kconfig
@@ -392,7 +392,7 @@ config SENSORS_GL520SM
 
 config SENSORS_CORETEMP
 	tristate "Intel Core/Core2/Atom temperature sensor"
-	depends on X86 && EXPERIMENTAL
+	depends on X86 && PCI && EXPERIMENTAL
 	help
 	  If you say yes here you get support for the temperature
 	  sensor inside your CPU. Most of the family 6 CPUs
diff --git a/drivers/hwmon/coretemp.c b/drivers/hwmon/coretemp.c
index caef39c..2d7bcee 100644
--- a/drivers/hwmon/coretemp.c
+++ b/drivers/hwmon/coretemp.c
@@ -33,6 +33,7 @@
 #include <linux/list.h>
 #include <linux/platform_device.h>
 #include <linux/cpu.h>
+#include <linux/pci.h>
 #include <asm/msr.h>
 #include <asm/processor.h>
 
@@ -161,6 +162,7 @@ static int __devinit adjust_tjmax(struct cpuinfo_x86 *c, u32 id, struct device *
 	int usemsr_ee = 1;
 	int err;
 	u32 eax, edx;
+	struct pci_dev *host_bridge;
 
 ...
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